This invention relates to error detection and correction and in particular to symbol error correction. A symbol is a subset of adjacent bits in a data word and the term package error detection and correction is sometimes used. In particular, this invention relates to reduced redundancy symbol error detection and correction code which has particular application to a memory organized on a b-bit per chip basis where the symbol size is b.
Applicants earlier U.S. Pat. No. 4,464,753 which is assigned to the same assignee as this application shows a general scheme for package error correction and an application to a symbol size of 2. U.S. Pat. No. 3,634,821 also shows a b-adjacent code.
Applicants earlier U.S. Pat. No. 4,509,172 assigned to the same assignee as this application shows a code for package error detection with reduced redundancy. However, this patent does not show package error correction and is different from the present invention.
A package error correction system for a 4 bit per package memory is shown in U.S. Pat. No. 4,617,664 assigned to the same assignee as this invention. This patent does not show two symbol error detection, however. In addition, the present invention represents a reduced redundancy over the system shown in the patent.
Other prior art U.S. Pat. Nos. known to Applicant are 3,755,779; 3,745,525; 3,623,155 and 3,629,824 none of which, however, anticipate the present invention.
U.S. Pat. No. 4,661,955 assigned to the same assignee as the present invention, shows a system for detecting and eliminating soft errors in a package ECC.
The IBM Technical Disclosure Bulletin also contains articles dealing with package error detection or correction. In particular, "SEC-DED Codes With Package Error Detection Ability", November 1979, pages 2356-2359; "Optimized Error Correction/Detection For Chips Organized Other Than By-1", March 1982, pages 5275-5276 and "Dual-Mode Error Correction and Error Detection", June 1985, pages 55-58 illustrate the state of the art but do not anticipate the present invention.
Because of the cost of a system, such as a memory, is dependent on the number of bits required for error detection and correction, any reduction in the resource required for the system will produce a cost savings. Therefore, it is desirable to have an improved error correction and detection system with reduced redundancy to save on costs in a system, such as a memory.